1. Field of the Invention
This invention relates generally to substrate fabrication, and more particularly to semiconductor wafer cleaning after etch operations.
2. Description of the Related Art
As is well known, semiconductor devices are fabricated from semiconductor wafers, which are subjected to numerous processing operations. These operations include, for example, impurity implants, gate oxide generation, inter-metal low K dielectric, metallization depositions, photolithography pattering, etching operations, chemical mechanical polishing (CMP), etc.
FIG. 1A illustrates a cross-section partial view of a layer stack, representing the layers formed during the fabrication of a typical semiconductor integrated circuit (IC) device. The layer stack typically can have numerous layers in the stack. Only a top portion of the stack where processing is taking place is shown. Metallization layer 13 typically includes aluminum, copper or one or more of a variety of known aluminum alloys such as Al—Cu, Al—Si, and Al—Cu—Si. Also shown is an anti-reflective coating (ARC) layer 14 that is formed over metallization layer 13. As is well known in the art, ARC layer 14 is typically composed of Ti, TiN or TiW. Generally speaking, ARC layer 14 is useful in preventing light used in photolithography processes from reflecting and scattering off of the metallization layer 13 surface. A low K dielectric layer 16 is then formed over the ARC layer 14. In this simplified example, a photoresist layer 18 is then spin coated over the low K dielectric layer 16 and patterned to define windows where etching is desired. As is well known, photoresist layer 18 represents a layer of conventional photo-sensitive resist material that may be patterned using patterned reticles and a stepper that passes selective light waves onto the surface of photoresist layer 18. The layers of the layer stack are readily recognizable to those skilled in the art and may be formed using any number of known deposition processes, including chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) such as sputtering, spin coating, etc.
At this point, an etch operation 20 is performed in order to selectively remove portions of the low K dielectric layer 16. In this example, a feature 17 is etched into the low K dielectric layer 16, and the feature 17 may be a trench, a via hole, or any other geometric pattern. Preferably, the etch 20 is chosen to have good selectivity to enable efficient etching of the low K dielectric 16 layer. During the etching operation, however, polymer formation 22 is known to occur on the sidewalls of features 17 being etched.
FIG. 1B shows the a cross-section view of a layer stack after an ashing operation 23 is conducted after the plasma etching operation. The ashing operation serves to remove the photoresist layer 18. Residue 27 is left after the ashing operation 23. Residue 27 may include both etching residues and ashing residues. The actual composition of the residue 27 depends upon the material being etched, the chemistry used for the etching, the chemistries used for ashing, and the underlying material. Thus, the material representing the residue 27 will generally be a low K dielectric material containing some of the etch chemistry components, ashing chemistry components, carbon from the photoresist, and organic residues. The residue 27 may extend along the sidewalls and up onto the photoresist layer 18. In addition, a residue crown 27′ may form on the surface of the low K dielectric layer.
To remove the residue 27, it is conventional practice to move the wafer into a chemical bath containing liquids that are designed to remove the residue 27. Although chemical bath rinsing has worked in the past, the demand for smaller device features has increased the need to have a very clean environment at every step of a fabrication process. Unfortunately, bath rinsing is inherently an unclean environment. The residue 27 being rinsed in the bath may therefore contaminate the bath, and the removed material may be deposited or can attach to other parts of a wafer or to other wafers being processed through the bath.
In addition, conventional methods of cleaning which are generally designed to remove silicon oxide residues after etching and ashing are not effective to clean low K dielectric residues. This is because oxides are hydrophilic and form different types of residues which require different types of cleaning methodology. In contrast, low K dielectrics are hydrophobic and are engineered to have a very low dielectric constant.
In view of the foregoing, there is a need for improved methods that will enable efficient removal of etching and ashing residues that are formed when generating low K dielectric features. The removal should be efficient enough to remove the contaminants and prevent further contamination of other surface areas of a wafer being processed.